In the absence of a better answer, I'll try answering my own question here - hopefully someone might find it useful. However, if someone has a more authoritative answer please go ahead.

Answer 1: As suspected, the endianness is taken from the input elf file by default (it's defined in the elf header). In case that endianness is not defined, or you want it different to the input file then I think newer versions have an option --verilog-data-endianness to set this. Unfortunately, the version that I have access to does not support this, so I can't comment. In any case, since the output file is plain text, with data in hexadecimal format, it is easy enough to change endianness with some text processing.

Answer 2: This is a bit of a guess, but I think this is just how the mem file is interpreted. I was thinking of the address as just byte address, but if you think of it as an offset, it makes more sense. For example, if width is 1 (i.e. bytes) the "address" is the byte offset; if the width is, say 4, (i.e. 32-bit words) then the "address" is the word offset - which is the byte offset / 4 in this case. At least, that's how I'm rationalizing the behaviour.