I'm sure you've already done this, but anyone else can search for "stm32f103 bus matrix" or look at AN3427 (pg. 12 of Rev. 1) to get a good idea of the bus layout.

There are three core buses: I-bus, D-bus, S-bus. All of them can access SRAM. (S-bus does not touch flash but is the only core path to the peripherals.) The path where the I-bus connects to flash is called ICode, while the path where the D-bus accesses flash is called DCode. (Prefetching is performed on the ICode bus.)

At the same time, the reference manual (RM0008 Rev. 21) explains that SRAM is generally accessed via the S-bus.

What explains the connection between SRAM and I-/D-bus on a Cortex-M3? That's a head scratcher… or perhaps a typo? (Even exceptions use the appropriate bus separation.)

(Aside: There is a discussion about ST's Cortex-M3 cores where an Arm architect explains the SRAM is dual-port, read-only to ICode and read/write to DCode. I'd need a lot more context to figure out what that's supposed to mean.)

(Second aside: On the STM32F3, there is CCM SRAM that can only use I-/D-bus.)

(Third: On STM32 Cortex-M4 targets, SRAM can relay instructions to the core using either system or instruction bus, but I-bus is more efficient. This is explained in RM0390.)