x and y are integers (represented by the tools using a LOT of bits, I think 32 as default for systemverilog), so if x = 1 (integer) your tools might translate that to 32'h0000_0001 hence ~x might end up as = 32'hffff_fffe. Is that reasonably interpreted as "True" or "False" ? It's a non-sensical question to ask the synthesis tools to begin with.

Summary: Don't do boolean logic on integers! Do boolean logic on type "logic" or "wire" etc...