According to Arm Architecture Reference Manual for A-profile architecture, it's impossible.

In the section E1.3.1.1 Advanced SIMD views of the register file, the document describes the registers under aarch32 as following:

Advanced SIMD can view this register file as:

• Sixteen 128-bit quadword registers, Q0-Q15.

• Thirty-two 64-bit doubleword registers, D0-D31.

These views can be used simultaneously. For example, a program might hold 64-bit vectors in D0 and D1 and a 128-bit vector in Q1.

However in the section B1.2 Registers in AArch64 Execution state, the document describes the registers under aarch64 as following:

32 SIMD&FP registers, V0 to V31. Each can be accessed as:

• A 128-bit register named Q0 to Q31.

• A 64-bit register named D0 to D31.

• A 32-bit register named S0 to S31.

• A 16-bit register named H0 to H31.

• An 8-bit register named B0 to B31.

• A 128-bit vector of elements. See SIMD vectors in AArch64 state.

• A 64-bit vector of elements. See SIMD vectors in AArch64 state.

Where the number of bits described by a register name does not occupy an entire SIMD&FP register, it refers to the least significant bits.