These answers are all good. An explanation of WHY there is a 4-level page table though...

x86 and x86-64 use 4KB pages; x86 (32-bit) gets 1024 32-bit entries in a page. So the first level points to 1024 page tables; the second level each of those (up to) 1024 has 1024 4KB pages.. that covers the whole 4GB address space. 2^12 is 4096 (4KB), so out of those 32 bits per page table entry, 20 bits are used for the address and the other 12 are used for various flags (for example, a bit that the OS can clear and the hardware sets if a page is accessed, the OS can then know if a page has been accessed, a user/supervisor bit to prevent an application from accessing an OS-owned page, a bit to set a page read-only, etc.)

64-bit, it's 4 level (or now in some cases 5...) because with 64-bit addressing, and still 4KB pages, you now have only 512 entries in a page (since each entry is 64 bits instead of 32), while having far more potential pages in a 64-bit system (since it has 16 exabytes maximum memory instead of 4GB.) So you need lots and lots of page tables if you have lots and lots of RAM to keep track of.

Later model (like Pentium or Pentium Pro on up or so if I recall?) x86 supports 4MB pages. And x86-64 supports 2MB and 1GB pages as options, and Linux has "Huge page" support to support using this. A few memory-intensive applications turn it on if available... these can use fewer levels of page tables so there's some small speedup from the lower overhead. But there's a lot of overhead for every little memory allocation something needs only being able to grab 2MB at a time, having swap happen 2MB at a time, etc., which is why 2MB pages have not just been set as the default.