Follwoing you need to make.

• Make a logical code in vhdl/verilog in Vivado.
• Make an AXI interface for it (or AXI Lite) and define some read/write registers in it which are connected to your vhdl/verilog businness logic in Vivado.
• In Vivado block design, use it as an AXI IP block and connect it to an AXI interconnect to able to reach it from PS of ZynqMP.
• Make an XSA export from Vivado.
• Use them from SW
  • Open XSA in Vitis and you can develop any simple and easy bare-metal SW in C code for reading/writing these AXI register in your IP.
  • Build a full Linux OS for ZynqMP and read/write your AXI registers via Linux UIO drivers from any language like Python, bash, perl, C/C++ so on ...