For synthesizable behavioral/RTL models in Verilog, the chosen RTL synthesis tools of your choice can map each division operator in the dataflow graph representations of your synthesizable behavioral/RTL Verilog models to a divider circuit (digital/logic circuit for division) for logic synthesis (i.e., sequential logic synthesis and combinational logic synthesis).

During logic synthesis's technology mapping phase, it will map the divider to a chosen implementation (as a soft macro blocks) of a divider in your standard cell library. The selection is based on your preferences, in terms of optimization objectives (or cost functions) and constraints (e.g., in terms of performance, number of logic cells used, and energy efficiency). This avoids unnecessary combinational logic optimization of pre-optimized soft macro blocks of divider circuits.