The answer from toolic provides the gist of it.
My other answer provides more details about this process for RTL synthesis, by converting it to a tuple/pair of control flow graph and dataflow graph (CFG, DFG), or its hybrid control/data flow graph (CDFG).
Reference: https://stackoverflow.com/a/79284832/1531728
However, I would prefer to use the term RTL synthesis to describe the transformation from synthesizable behavioral/RTL Verilog models into structural Verilog models at the gate/logic level.