I think you should try to understand the tag-index-offset concept first.

[11010|offset] and [01010|offset] addressed cache lines are completely different. They point to different cachelines on memory. Indexing just helps the placement of the datas in caches. 2 addresses with same indexes, means you should place these datas to the same row in the cache. If tags are different and you are using a set-associative/full-associative cache, you can place 2 datas in the same indexed row but different ways(columns), but they points different datas.

Your answer hidden in your question. You are not sure the difference tag bits make. To understand cache coherence, first you should completely understand the basics of the caching.

Some other advice, for exclusive state, you should be sure that you can claim a cache line is exclusive before you do. You can be sure by 2 different ways, you can send an invalidation, or you get an exclusive response from bus. That differs by the bus protocol you are using for cache coherence.

Concept is not simple that study on it like an hour and completely understand.