Any help will be greatly appreciated.

I am able to reproduce your actual simulation result for final_result on different simulators. That means the discrepancy is not due to the Vivado simulator.

You can verify this yourself by running your code on other free simulators on EDA Playground. You will see that the simulators are just doing what you told them to do with your Verilog code.

You need to review the algorithm you used in your code (the bit shift, the XOR, etc.).

Also, to debug your code, you can temporarily add some $display statements inside the for loop to show the intermediate values of p as a function of i. For example:

        for (i = 0; i < N; i = i + 1) begin
            if (a[i] == 1'b1) begin
                p = p ^ (b << i); // XOR and shift
                $display($time, "   i=%02d      p=%b 34: 0", i, p[34:0]);
                $display($time, "   i=%02d      p=%b 69:35", i, p[69:35]);
            end
        end