Any help debugging would be greatly appreciated

Programming Verilog code into an FPGA is a methodology with several steps, but you are skipping some of them:

• Using good Verilog coding style for synthesis
• Simulating the Verilog code
• Synthesizing the Verilog code and thoroughly reviewing all synthesis reports

I see some potential problems in the Verilog code snippet that you posted into the question:

• Using blocking (=) instead nonblocking (<=) assignments in the always block.
• Assigning the same signal (such as bit) in independent if statements

Nonblocking assignments should be used to model sequential logic. Using blocking assignments there will likely cause Verilog simulations to produce unexpected results.

You should make yourself familiar with synthesizable good practices. Your FPGA toolchain documentation might have some good guidelines.

You should simulate the Verilog code before synthesis, if you are not already doing so. You need to create a Verilog testbench if your toolchain does not create one for you. You need to drive the inputs with some basic patterns and look at waveforms of your outputs to make sure they behave as expected.

After you synthesize the code for the FPGA, you must review all the synthesis reports. Check for error and warning messages. Sometimes these are buried, so you might need to go looking for them.

for loops seem to not be synthesizable on the FPGA

That is one possibility. Another possibility is that you have a syntax error in your for loops. It is much simpler to debug syntax errors in simulation.