msr writes a system register, which in general doesn't count as a memory write, so normally memory synchronisation instructions like dmb and dsb won't work for them. If you want to be sure that later instructions aren't re-ordered to before the mrs, you need an isb.

(To prevent previous memory accesses to be re-ordered after the mrs, in general I would have expected a dsb before the mrs, but perhaps that's not needed for ttbr1_el1?)

Without the isb, tlbi could execute before the mrs is finished and act on the wrong TLB entries.

The dsb is needed to prevent memory accesses after the tlbi instruction to be executed too early, before the tlbi. Assuming the tlbi is needed (which I think isn't in general after changing ttbr1_el1), without the dsb those memory accesses could use stale TLB translations that haven't been flushed by the tlbi yet.

The last isb is needed to make sure that the following instruction see the effects for the previous ones. I think that's only needed if the following instructions need to be refetched with the new TLB settings too. So the dsb is to sync later memory accesses, while the isb syncs future instructions.

Reasonably well explained here: https://developer.arm.com/documentation/100941/0101/Barriers