Relative to trying to use both clock edges it's probably not a bad idea, assuming you can somehow make your code work like that. In general though it's a bad approach because FPGAs are designed for standard synchronous logic so you may find yourself running out of resources unusually quickly or having a hard time with timing.

I'd suggest using a standard clock at 2x the rate of your 'single cycle' clock, and treating each pair of rising edges as if the first was the rising edge and the second as if it was the falling. If necessary, include another signal that toggles on each 2x clock so you can tell which edge of the single cycle clock is coming next.