Library IEEE;

USE ieee.std_logic_1164.all;

ENTITY en_8_3 IS

PORT (DIN BIT_VECTOR(7 downto 0);

Y:OUT BIT_VECTOR(2 downto 0));

END en_8_3;

ARCHITECTURE dataflow OF en_8_3 IS

BEGIN

Y(2) <= D(7) or D(6) or D(5) or D(4);

Y(1) <= D(7) or D(6) or D(3) or D(2);

Y(0) <= D(7) or D(5) or D(3) or D(1);

END dataflow;