In all cases some sort of IO primitive (IOBUF/IBUF/OBUF/etc.) is required. If you don't explicitly instantiate one, the synthesis tool will infer one. In the case of your Verilog code, it can infer the IOBUF properly. However the block design tool isn't designed to do that and doesn't generate code that allows the synthesis tool to infer an IOBUF, so you have to instantiate one manually with the utility buffer block.