When using the HSI directly as the PLL input on STM32F303xE devices, you also have to configure the "PREDIV" correctly. Simply setting the PLLSRC bits to "01" (HSI) in CFGR is not enough, because on these parts the pre-divider (1..16) is controlled in a separate register (RCC_CFGR2). If you do not set PREDIV to 1 there, the clock tree can become invalid and your code will lock up waiting for the PLL to become stable.