I also have posted to the infineon forum and got an answer there that solved the problem!

The problem was that the offset of 0xFED4 was supposed to be used for communicating with the TPM via MMIO. For direct communication via SPI the offset is just 0xD4. After changing the offset and adding a 0x00 dummy byte before the actual transfer for timing I am now able to conduct write operations!

If anyone is wondering, this is the exact bit stream I'm sending for a successful write operation (to enable all interrupts):

uint8_t TxData[] = {
    0x00, 0b00000011,   // write bit + size of transfer (4 bytes)
    0xD4,           // specified offset
    0x00, 0x08,     // TPM_INT_ENABLE_0 register (locality 0)
    0x0F, 0x00,
    0x00, 0x80
};

Here is the link to the infineon forum thread.