This one is sneaky, because it is not explicitly mentioned anywhere in the reference manual (RM0490). The only clue given is by looking at the system architecture diagram on page 40:

For this chip, the GPIO ports are directly connected to the core, not the AHB bus, so the DMA has no access to them. It would seem that they opted for this layout to improve latency.

To trigger pins through DMA writes, you have to disable the preload of CCRx channels, and write values at the extremities (0 or ARR) to cause the outputs to flip accordingly.