I have been looking into exactly this. I have implemented all of the architecture using System Verilog and here my interpretation.

During the tock phase (posedge):

1. All the registers in the CPU (A, D and PC) commit to a new value. That means the output is the old value but the next cycle they will output a new value. This could be thought as of the assignment part of the instructions.

During the tick phase (negedge)

1. The registers are outputting the new value and the instruction will be executed. Think of it as the the right part of the instruction.

For example you want to do A=A+D

On the negedge

The current value of A and D Will be summed up.

On the posedge

The new value coming from the ALU (A+D) is commited to the A register, since no jump condition has been specified the PC will simply commit an increment value of 1.

On the next negedge A will output the right value, and new instruction will come in.