Besides the value for Q divider as Clifford wrote above, in 'L476, all three PLLs share clock source - see the clock tree diagram in RCC chapter of RM0351. So, you have to set up that source in RCC_PLLCFGR.PLLSRC (and the M divider in RCC_PLLCFGR.PLLM).

Also, there is no such field in RCC_PLLSAI1CFGR (so there's no point in setting 0b01 there).

Also, keep in mind the fact that there's only one shared clock source for PLLs, when setting up the remainning PLLs.

JW