Found it, apparently the check is already done by ARM's address alignment. There's no mechanism for handling page-boundary crossing in itself since the virtual addresses are already designed in a way where that kind of situation wouldn't happen.

This design is what prevents any potential page-crossing once the translation process begins, and that makes sense since it occupies the bytes that can only be covered by the access size in the case where all bits are 1 except the 0th and 1st index (for a word access), preventing any kind of bit overflow around the last indexes of the page.

So in the example of a 4-byte access, the address MUST be divisible by 4 so that it guarantees there's enough space at the page ending for no crossing to occur. It's the same story with a 2-byte access, where it must be divisible by 2.

It was my 3rd hypothesis apparently, but I wish the ARM documentation would specify why the alignments where designed and what they are for. It took me a lot of mental bit twiddling and documentation digging to find this out. However, alignment checking is optional, so I'm not sure what happens in the case where it's disabled and an actual page crossing happens.