1 & 2 -

Clear, in and load variables are condition variables in your gen_bits module. But, you define this variables as a bit, 2-stated memory variable in your testbench.

So, any if/else/case block which checks these values in positive edge of the clock on your testbench, will get the left side value of these variables at the positive edge clock as expected.

Because you are reading a memory block end of the day, not checking an output of a combinational circuit.