Sorry for the English, it is done by Google translator.
I program in assembler for reasons of time-critical sequences. That is why I carefully studied the machine run of instructions and I have this information because I encounter the same thing.
The processor determines whether the interruption occurred only in the first time phase of processing and executing the instruction. Then no more. However, each instruction is definitely executed only in the final machine cycle of executing the instruction. It is logical, first the code is loaded, it goes to the instruction decoder and so on. Only at the end is everything executed and valid (for example, setting the port to H or L). And when the processor detects an interrupt request in the first time phase, this instruction where the interrupt is detected is still processed, but in the following instruction the interrupt is processed in such a way that the processor cancels the entire queue that it has unread and executes this instruction as a NOP and is terminated by a jump to the ISR. So it is not executed anymore. It is executed only after returning back.
So a timing mismatch can occur. The processor executes the "disable interrupt from peripherals" instruction. In the first time phase of the instruction, it is tested whether an interrupt has occurred. It does occur, but only a short moment after this HW test. Therefore, the processor in the first time section of processing the "disable interrupt from peripherals" instruction does not recognize the interrupt, it occurs only a moment later, but the internal circuits still start to set up. They start to set up because the interrupt will be disabled when it completes this instruction.
Next. The "disable interrupt from peripherals" instruction is followed by another instruction. In its first time section, according to the previous setting of the internal circuits, it is determined that there is a request for an interrupt from the periphery and according to the rule that an instruction that recognizes an interrupt in the first time phase of its processing is also executed. Therefore, it is necessary that the instruction after the "disable interrupt from the periphery" instruction be a NOP instruction.
I have traced the behavior of the processor as follows:
The interrupt occurs before the "disable interrupt from the periphery" instruction. This instruction identifies the interrupt in the first time phase and is executed. The instruction after it is not executed, the ISR is executed.
The interrupt occurs after the "disable interrupt from the periphery" instruction is completed. The interrupt is not executed, it is disabled.
The interrupt occurs within the time frame of the "disable interrupt from the periphery" instruction. Between the first time phase of the instruction (where there is a test to see if the interrupt has occurred) and its completion (when the interrupt is definitely disabled). Therefore, after completion, the interrupt is disabled, but it is recognized only by the following instruction, which is also executed. It must be a NOP instruction, if it cannot be executed.
This is how it behaved for me too. And since in case number three it is a very short time interval, the probability of a match is small and therefore it sets it occasionally.
I am not saying that I am right, but my program behaved exactly as I described. Please study chapter 3.0 INTERRUPT PROCESSING TIMING in DS70000600D. From that I came to my conclusions.