You are asking 3 questions which makes answering difficult:

Question 1: Are these two VHDL processes synchronous?

Processes can't be synchronous, they are a construct of VHDL, only electrical signals can be synchronous.

Question 2: How should I create a slow clock derived from a (possibly much) faster clock without creating a gated clock, and while maintaining 50% duty cycle on slow_clk?

You should work with a clock enable signal: This means all flipflops should be connected to the same clock, in your case to the 12 MHz clock. The flipflops which must be clocked slower should be additional connected to a clock enable signal, which is active at each 12th clock edge of the 12 MHz clock (of course this solution has no signal with a 50% duty cycle).

Question 3: Do I create a new clock domain by using slow_clk_q in the sensitivity list of sm_proc, or are the two processes actually synchronous to clk?

A new clock domain is not created by a sensitivity list, a new clock domain is created by checking the data signal slow_clk_q for a rising edge. This will connect slow_clk_q to a clock input of a flipflop at synthesis and is a not recommended design practise especially for FPGAs but also for ASICs. Nevertheless this new clock domain will be synchronous to your 12 MHz domain, but exchanging data signals between this 2 clock domains is difficult, as the edge of your slow clock will not happen at the same time as an edge of our 12 MHz clock, but a short time later.

Your questions concentrates on the Item "synchronous". As long as you have only 1 clock source (in your case the 12 MHz clock) all derived signals (for example your slow_clk_q) are synchronous to this clock, because they only can change their value after a rising edge of your single clock source. Only if you have a second independent clock signal (not created by your 12 MHz clock but somewhere else), then you will get a second clock domain which is asynchronous, this means by observing one clock you cannot predict at what time the other clock will have a rising edge.