79755906

Date: 2025-09-04 15:24:02
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It should be 256 bytes.

From ARM

The C++ 17 specification has two defined parameters relating to the granularity of memory that does not interfere. For generic software and tools, Arm will set the hardware_destructive_interference_size parameter to 256 bytes and the hardware_constructive_interference_size parameter to 64 bytes.

https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/CCSIDR-EL1--Current-Cache-Size-ID-Register

For LLVM, it's here

Before this change, we would set this to Clang's default of {64, 64}. Now, we explicitly set it to {256, 64} which matches our ARM behavior for ARMv8 targets and GCC's behavior for AArch64 targets.

https://github.com/llvm/llvm-project/commit/bce2cc15133a1458e4ad053085e58c7423c365b4

* this is not in Xcode 26(LLVM 19.1.5) yet, it needs LLVM 21.1.0

For GCC, it's already been there for 4 years

He proposed 64/128 for generic AArch64, but since the A64FX now has a 256B cache line, I've changed that to 64/256.

https://github.com/gcc-mirror/gcc/commit/76b75018b3d053a890ebe155e47814de14b3c9fb

* "He" refers to JF Bastien, author of https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0154r1.html

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Posted by: Trout.Z