Most MMIO accesses in modern CPUs use the same core, memory interconnect path as normal DRAM but are marked uncacheable, so caches are bypassed (no allocation or tag lookup). Buffers like load/store and write-combine still handle them. Some low-bandwidth control/status registers may use separate sideband ports with dedicated buffers. So gem5’s approach of traversing the cache hierarchy as uncached memory is a reasonable model for real CPUs.